1. Field of the Invention
The present invention relates to the field of integrated circuits and, more particularly, to testing and verification of integrated circuit designs.
2. Description of the Related Art
Modern integrated circuits (ICs) are developed through the use of hardware description languages (HDLs). HDLs, such as VERILOG, VHDL, and the like, allow developers to create software-based representations of circuit designs. One advantage of using an HDL is the potential for code reuse from one design to another. This concept has been realized with the commercial availability of intellectual property (IP) cores. In general, an IP core refers to a software representation of a semiconductor, or a portion of a semiconductor, that provides a processing function.
Before HDL logic is made available for commercial use, it must be thoroughly tested and verified. The HDL logic must be tested to ensure that it functions properly and as expected, particularly as defined in the design specification. Typically, this testing is performed using a verification environment such as a testbench. A verification environment is comprised of HDL descriptions, which specify and verify the behavior of a device under test (DUT), as well as an HDL simulator, which executes the HDL descriptions. In this case, the DUT is HDL logic such as one or more IP cores. The verification environment can specify the connections, events, and input signals for different combinations of transactions involving the DUT. In general, the verification environment provides a pre-determined input sequence to the DUT and observes the response, or output from the DUT.
One function that must be adequately tested is the ability to generate interrupt signals. The use of interrupt signals allows the device intended to receive such signals, referred to as the target device, to continue processing data until such time that an interrupt signal is received from a sending device. The target device is relieved from having to continually poll the sending device for error conditions. Within a given device, there may be many different types of events which cause an interrupt signal to be generated. Most devices, however, have a single interrupt pin, and as such, generate a single interrupt signal. A status register commonly is provided which outputs additional information as to the reason why the interrupt was generated. The target device can access the status register upon receiving an interrupt signal to determine the cause of the interrupt signal. In any case, to test this capability, the verification environment must ensure that the DUT generates an interrupt signal under the proper circumstances.
Many modern devices have an architecture that is pipelined to some degree. Though pipelining can provide computational efficiencies, it also can create a situation in which a delay occurs between the time data is written to a device and the time the data is processed within the device. Predicting these latencies is difficult as the insertion of first-in-first-out memories (FIFOs) between processing stages, or pipelines, within the device makes the latencies non-deterministic with respect to the data input. When throttling is used, it becomes even more difficult to predict latencies. This, in turn, makes it difficult to determine the relationship between the time a trigger is introduced into the DUT, which causes an event requiring event handling, and the activation of the interrupt signal in response to the trigger.
As used herein, the term “throttling” refers to the regulation of inputs from the verification environment to the DUT. The term is derived from an analogy between the regulation of data provided to a DUT and the regulation of fuel provided to a vehicle, i.e. using the throttle. In illustration, input to the DUT can be provided at “full throttle”, with no delay between inputs, or with a scaled back throttle such that some amount of time delay is introduced between inputs depending upon the degree of throttling introduced by the verification environment. When sufficient time is included between inputs, a stall condition can arise where one processing stage of the DUT is dormant while awaiting new input for processing.
Further complicating the evaluation of event handling, the resolution of an event can take more than one clock cycle. During testing, this can create a situation in which a DUT generates an interrupt signal responsive to a trigger input. The interrupt signal remains high while the event is handled. Before the event is completely handled and the interrupt signal is returned to a low state, another trigger may be provided to the DUT, causing the DUT to generate a second interrupt signal. In consequence, the interrupt signal remains continuously high. It is unclear, however, when the interrupt signal is flagged in response to the second trigger. As a result, multiple events can be flagged or marked by a single interrupt signal.
In illustration, FIG. 1 is a signaling graph depicting an interaction between a verification environment and a DUT involving several different trigger conditions. The signaling graph illustrates a scenario in which two different triggers, triggers 1 and 2, are introduced into the DUT at known times by the verification environment. The external throttling graph line indicates that a minimal amount of throttling has been introduced between the occurrence of trigger 2 and the time the DUT activates the interrupt signal. In terms of testing and/or verification, the verification environment is aware that two different trigger conditions have been introduced into the DUT.
Though FIG. 1 indicates that the interrupt signal was triggered by the DUT, there is no indication as to whether the interrupt signal was flagged responsive to trigger 1 or trigger 2. The non-deterministic nature of the DUT can make evaluations difficult. Further, assuming that an analysis of the test data does reveal that trigger 1 was the cause of the interrupt signal being activated at time T, FIG. 1 does not indicate when trigger 2 was signaled at some point after time T. Determining the portion of the interrupt signal that is attributable to each trigger is a difficult task for conventional testing and/or verification techniques, which tend to be single-threaded in nature.
FIG. 2 is a signaling graph illustrating another interaction between a verification environment and a DUT in which several triggers of a same type are introduced over a short interval. As shown, the external throttling indicates that the DUT is stalled three times with the third stall being longer in duration than the others. Through analysis of the test results, it may be possible to determine that trigger 1A caused the event handling indicated by the interrupt signal. Still, using conventional verification techniques, it is difficult to determine whether trigger 1B or trigger 1C was handled.
It would be beneficial to provide a technique for verifying event handling which overcomes the limitations described above.